Modern electronic equipment uses digital semiconductor integrated circuits for operation thereof. The digital semiconductor integrated circuits receive inputs from various sources, e.g., pushbuttons, sensors, etc., and have outputs that control operation of the equipment based upon the various inputs thereto. The inputs and outputs of the semiconductor integrated circuits may be subject to undesirable high voltage electrostatic discharge (ESD) in addition to the desired input or output signal level. The ESD, characterized by fast transient high voltage discharges, may be from static electricity generated by a user of the equipment, equipment handling, power supply voltage transients and the like. An ESD event may create a sufficiently high voltage to cause destructive breakdown of transistor devices connected to the inputs and/or outputs of the semiconductor integrated circuits.
Semiconductor integrated circuits are becoming functionally more capable and are operating at faster speeds. The increased functional capability is the result of higher transistor count in each integrated circuit, thereby allowing the operation of more sophisticated software and/or firmware to produce the many features available in the equipment. The faster operating speeds further enhance the operation of the equipment. In order to keep integrated circuit die size within a reasonable cost, the electronic circuits therein must be more densely concentrated in as small an area as possible, thus the many transistors making up the electronic circuits within the integrated circuit must be made as small as possible. As these transistors become smaller and smaller, the spacing of the parts of each transistor, e.g., source, gate, drain, becomes smaller, as does the dielectric thickness of the insulation between these parts. The extremely thin dielectric is very susceptible to damage by excessive voltages present in an ESD event that may cause destructive breakdown of an input and/or output device. Also, as operational speeds increase, the need for low capacitance structures becomes more important.
Various voltage protection circuits have been used to limit the peak voltage at an input and/or output of an integrated circuit. Attempts have been made to incorporate ESD protection within the integrated circuit, but are either not very effective, and/or require a significant amount of area within the integrated circuit die. When an ESD event occurs, some ESD protection circuits will remain conductive to ground at a lower voltage than what initially triggered conduction in the ESD protection circuit. This is called “snapback” and is undesirable, especially when an input and/or output is adapted for high voltage operation (voltage being higher than a normal logic voltage level). Use of the breakdown voltage of a diode for ESD protection has no snapback problems but lacked sufficient current handling for most ESD events.
Therefore, what is needed is an ESD protection circuit integral within the integrated circuit die that is effective is protecting sensitive input and/or output circuits from an ESD event that may cause destructive breakdown, has enough current handling capabilities during the ESD event and does not snapback from the ESD event occurrence.